Infrared detector elements and methods of forming same

ABSTRACT

Infrared detector elements and methods for forming infrared detector elements in which the top metal layer of CMOS circuitry of the detector element is employed as a lead metal reflector for the infrared detector.

This patent application claims priority to copending U.S. Provisional patent application Ser. No. 60/762,252, filed Jan. 26, 2006, and entitled “SYSTEMS AND METHODS FOR INTEGRATING FOCAL PLANE ARRAYS” by Syllaios et al., the entire disclosure of which is incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates generally to infrared detector elements, and more particularly to microbolometer infrared detector elements.

BACKGROUND OF THE INVENTION

Infrared (IR) detectors are often utilized to detect fires, overheating machinery, planes, vehicles, people, and any other objects that emit thermal radiation. Infrared detectors are unaffected by ambient light conditions or particulate matter in the air such as smoke or fog. Thus, infrared detectors have potential use in night vision and when poor vision conditions exist, such as when normal vision is obscured by smoke or fog. IR detectors are also used in non-imaging applications such as radiometers, gas detectors, and other IR sensors.

A variety of infrared detector types have been developed in the past. Many include a substrate having thereon a focal plane array (FPA), the focal plane array including a plurality of detector elements that each correspond to a respective pixel. The substrate contains an integrated circuit which is electrically coupled to the detector elements, and which is commonly known as a read out integrated circuit (ROIC).

Infrared detectors generally operate by detecting the differences in thermal radiance of various objects in a scene. That difference is converted into an electrical signal which is then processed. Microbolometers are infrared radiation detector elements that are fabricated on a substrate material using traditional integrated circuit fabrication techniques. Microbolometer detector arrays consist of thin, low thermal mass, thermally isolated, temperature-dependent resistive membrane structures. They are suspended over silicon ROIC wafers by long thermal isolation legs in a resonant absorbing quarter-wave cavity design.

Conventional infrared detector arrays and imagers operating at ambient temperature include microbolometer arrays made of thin films of hydrogenated amorphous silicon (a-Si:H) or amorphous vandium oxide (VOx). Other materials used for microbolometer arrays include films of various metal (e.g., titanium) and high temperature superconductors. For an array based on amorphous silicon, the detector pixel membrane is generally comprised of an ultra-thin (˜2000 Å) a-SiN_(x)/a-Si:H/a-SiN_(x) structure. The membrane is deposited at a low temperature nominally below 400° C. using silane (SiH₄) and ammonia (NH₃) precursors for the amorphous silicon nitride (a-SiN_(x)) layers, and using silane for the hydrogenated amorphous silicon (a-Si:H) layer. Hydrogen atoms from silane (SiH₄) molecules are the source of hydrogen content in the a-Si:H layer. A thin absorbing metal layer such as Titanium (Ti), Titanium-Aluminum alloy (TiAl), Nichrome (NiCr), black gold, or other material absorbing in the infrared band of interest, (e.g., at wavelength range of 1 micron to 14 micron), is inserted in the membrane to enhance infrared absorptance. Contact between the a-Si:H detector electrodes and the interconnect pads on a complementary metal oxide semiconductor (CMOS) signal processor of the ROIC is accomplished by thick aluminum tab metal interconnects.

After fabrication, microbolometers are generally placed in vacuum packages to provide an optimal environment for the sensing device. Conventional microbolometers measure the change in resistance of a detector element after the microbolometer is exposed to thermal radiation. Microbolometers have applications in gas detectors, night vision, and many other situations.

The primary factors affecting response time and sensitivity of microbolometers are thermal mass and thermal isolation. Microbolometer response time is the time necessary for a detector element to absorb sufficient infrared radiation to alter an electrical property, such as resistance, of the detector element and to dissipate the heat resulting from the absorption of the infrared radiation. Microbolometer sensitivity is determined by the amount of infrared radiation required to cause a sufficient change in an electrical property of the microbolometer detector element. Microbolometer response time is inversely proportional to both thermal mass and thermal isolation. Thus, as thermal mass increases, response time becomes slower since more infrared energy is needed to sufficiently heat the additional thermal mass in order to obtain a measurable change in an electrical property of the microbolometer detector element. As thermal isolation increases, response time becomes slower since a longer period of time is necessary to dissipate the heat resulting from the absorption of the infrared radiation. Microbolometer operating frequency is inversely proportional to response time. However, microbolometer sensitivity is proportional to thermal isolation. Therefore, if a specific application requires high sensitivity and does not require high operating frequency, the microbolometer would have maximum thermal isolation and minimal thermal mass. If an application requires a higher operating frequency, a faster microbolometer may be obtained by reducing the thermal isolation which will also result in a reduction in sensitivity.

To provide multi-spectral imaging capability, two physically separate infrared and visible imaging focal plane arrays have been employed. Images from the two separate focal plane arrays have been fused electronically using hardware and software. However, use of two separate focal plane arrays requires additional space and complicates the structure and circuitry of the imaging assembly.

Wafer level vacuum packaging is an enabling technology for low cost packaging of microelectromechanical systems (MEMS) devices that utilize a vacuum for operation. Such devices include IR bolometer detector arrays, RF resonant devices, and devices with moving parts that may be impeded by the presence of gas in the package. Alternatively, wafer level vacuum packaging is also usefully employed for packaging of devices that utilize a specific atmosphere and or pressure for mechanical damping. Some types of wafer level vacuum packaged MEMS devices are fabricated by attaching a lid wafer of optically transmissive material to a device wafer that includes MEMS devices (e.g., FPA devices) and associated circuitry. In such a configuration, the lid wafer provides an optically transmissive window above the MEMS devices.

MEMS devices that utilize a window that is optically transmissive in the IR spectrum may employ silicon-based material or other IR spectrum-transmissive wafer material for the material of the window of the lid wafer so that silicon-based device wafer and silicon-based lid wafer are thermally matched, i.e., having substantially same temperature coefficients of expansion (TCE). When performing wafer level packaging, little difference between TCE of a lid wafer material and TCE of a device wafer is allowable due to the relatively large diameter of the wafer and the large temperature change required for soldering (e.g., soldering with 80-20 gold-tin AuSn solder), anodic bonding (e.g., at temperatures greater than about 400° C.), and glass frit sealing (e.g., at temperatures from about 400 to about 500° C.).

However, those MEMS devices that require optical transmission in the visible spectrum utilize non-silicon-based window materials (i.e., materials that are primarily composed of a material other than silicon) that are optically transmissive for the visible spectrum. Due to thermal mismatch caused by differences in thermal expansion coefficients (e.g., TCE for silicon is 4.7×10⁻⁶/° C., TCE for ZnS=6.14×10⁻⁶/° C., TCE for ZnSe=7×10⁻⁶/° C.), lid wafers composed of such non-silicon-based visible spectrum-transmissive materials would be under high stress and fracture during bonding which would not be the case for silicon materials. Therefore, devices requiring optical transmission of the visible spectrum (e.g., for purposes of optical I/O) traditionally have employed standard hermetic ceramic or metal packages with an appropriate window bonded onto it, or bonded into a window frame that is then soldered or welded onto the package. However, such a configuration, results in an inherently costly package.

FIG. 20 shows a silicon substrate 2000 that includes CMOS circuitry layers 2030 formed thereon that are configured as individual detector element (or cells) 2060, 2062 and 2064 of an array area 2070 of a conventional focal plane array. In the illustrated embodiment, CMOS circuitry layers 2030 include first CMOS circuit metal layer 2002, second CMOS circuit metal layer 2004, and third CMOS circuit metal layer 2006, each of which are formed during CMOS processing. Third CMOS circuit metal layer 2006 is the top (i.e., last) CMOS circuit metal layer. CMOS circuitry layers 2030 also include first insulator layer 2003 (e.g., planarized oxide layer) between first and second CMOS circuit metal layers 2002 and 2004, and second insulator layer 2005 (e.g., planarized oxide layer) between second and third CMOS circuit metal layers 2004 and 2006, and passivation layer 2007 (e.g., planarized oxide/nitride passivation layer) adjacent third CMOS circuit metal layer 2006. CMOS nitride/oxide passivation layer 2012 is present over the last (or top) metal level layer 2006 in the CMOS circuitry, and input via structures 2016 are opened (e.g., via etching) in the final (or top) CMOS passivation layer to expose input pads 2050 of the top CMOS metal layer 2006.

In the conventional configuration of FIG. 20, a lead metal reflector layer 2014 is formed during post-CMOS bolometer fabrication as a non-CMOS metal layer over top CMOS passivation layer 2012. Also shown in FIG. 20 are electrically conductive metal via (plug) interconnects 2022 that are formed to extend through first insulator layer 2003 between first and second CMOS circuit metal layers 2002 and 2004, and electrically conductive metal via (plug) interconnects 2024 that are formed to extend through second insulator layer 2005 between second and third CMOS circuit metal layers 2005 and 2007. Electrically conductive metal via (plug) interconnects are, for example, TiW or copper.

SUMMARY OF THE INVENTION

Disclosed herein are systems and methods for providing multi-spectral image capability using an integrated multi-band focal plane array that in one embodiment may be configured as a single integrated multi-band focal plane array. In one embodiment, the disclosed systems and methods may be employed to simultaneously image in the visible spectrum and infrared spectrum using an integrated dual-band focal plane array, e.g., by imaging in the infrared spectrum using a suspended low thermal mass microbolometer structure and imaging in the visible spectrum using imager circuitry in the underlying read-out integrated circuitry of the focal plane array. In this embodiment, visible CMOS imaging circuitry may be placed within the CMOS circuitry used to readout the infrared microbolometer detector within the same pixel element. Other types of suitable visible imaging circuitry include, but are not limited to, charge coupled device (CCD) circuitry. The disclosed approach offers advantages to the existing conventional approach which is to use separate infrared and visible imaging FPAs and fuse the images electronically in hardware and software. In the practice of the disclosed systems and methods, other types of infrared detectors besides microbolometers may be implemented as alternative to microbolometers for multi-band FPAs including, but not limited to, ferroelectric detectors, pyroelectric detectors, thermal pile detectors, etc. Furthermore, integrated multi-band FPAs may be provided that are capable of imaging in more than two spectra, e.g., single integrated tri-band FPA that is capable of simultaneously imaging in the short-wave IR spectrum (from about 1 to about 3 microns), the mid-wave IR spectrum (from about 3 to about 5 microns), and the long-wave IR spectrum (from about 8 to about 12 microns).

As will be described further herein, a dual-band FPA may be configured in one exemplary embodiment so that visible radiation is allowed to reach underlying CMOS imaging circuitry through openings in the grid of suspended membrane of a diffractive resonant cavity (DRC) microbolometer. In another embodiment, a resonant cavity microbolometer design may be implemented which uses a continuous solid membrane structure with a single opening provided in the membrane directly over active CMOS imaging circuitry.

In one embodiment disclosed herein, visible complementary metal oxide semiconductor (CMOS) imaging circuitry may be placed within or otherwise integrated with CMOS circuitry that is provided to readout signals from an infrared microbolometer detector within the same pixel element of a focal plane array. In such an embodiment, an integrated dual-band FPA may simultaneously image in the visible spectrum using CMOS imager circuitry provided in the underlying ROIC and image in the infrared spectrum using a suspended low thermal mass microbolometer structure. In one exemplary embodiment, visible radiation may be allowed to reach the CMOS imaging circuitry through openings that may be provided in a grid of a suspended membrane of a diffractive resonant cavity (DRC) microbolometer. In an alternative exemplary embodiment, visible radiation may be allowed to reach the CMOS imaging circuitry through an opening provided in the continuous solid membrane structure of a resonant cavity microbolometer. In such an alternative implementation, an opening may be provided in the continuous solid membrane structure directly over the active CMOS imaging circuitry.

In those embodiments employing a DRC pixel, the thermal mass or heat capacity of the patterned DRC membrane structure is reduced relative to an unpatterned membrane structure, which has the effect or reducing the thermal response time of the suspended membrane structure. This characteristic may be implemented in one embodiment to enable high performing infrared bolometer elements with very short (e.g., less than about 5 milliseconds) time constant. Fast response pixels allow for higher frame rate operation of the infrared FPA (e.g., up to about 120 Hz). In addition, fast response time makes feasible the use of a periodic chopper together with a fast responding bolometer detector element.

In one embodiment disclosed herein, the last metal level in CMOS circuitry of a microbolometer may be itself employed as the lead metal layer. For example, the last metal layer may be configured to function as the lead metal reflector and input pad in the array area, and also to serve as part of the CMOS circuitry both within and outside the array area.

In one respect, disclosed herein is an infrared detector element, including: a microbolometer infrared radiation detector structure, the microbolometer infrared detector structure including a lead metal reflector. The lead metal reflector may include an at least partially exposed top metal layer of read out integrated circuitry (ROIC) that is configured as the lead metal reflector for the microbolometer infrared detector structure.

In another respect, disclosed herein is a focal plane array assembly, including: a substrate having a first side; and a plurality of microbolometer infrared detector elements, each of the plurality of microbolometer infrared detector elements including a membrane suspended over the first side of the substrate and a lead metal reflector disposed on the first side of the substrate between the suspended membrane and the substrate. The lead metal reflector for each of the microbolometer infrared detector elements may include an at least partially exposed top metal layer of read out integrated circuitry (ROIC) that is configured as the lead metal reflector for the microbolometer infrared detector structure.

In another respect, disclosed herein is a method of making a focal plane array assembly, including: providing a substrate having a first side; forming a lead metal reflector on the first side of the substrate, the lead metal reflector including an at least partially exposed top metal layer of read out integrated circuitry (ROIC) with an at least partially exposed and reflective upper surface; and forming a plurality of membrane structures on the first side of the substrate so that each of the membrane structures is suspended over the first side of the substrate with the at least partially exposed top metal layer of the ROIC disposed between the suspended membrane and the substrate.

In another respect, disclosed herein is a wafer-level packaged focal plane array assembly and a method of making the same. The wafer-level packaged focal plane array assembly may include: a device wafer that includes a substrate and a focal plane array assembly as described elsewhere herein; and a lid wafer. The lid wafer may be at least partially transparent to infrared radiation and may be assembled to the device wafer so that the lid wafer allows infrared radiation to reach the focal plane array assembly through the lid wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of an infrared detector according to one embodiment of the disclosed systems and methods.

FIG. 2 is a perspective view of a multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 3 is a perspective view of a lead metal reflector according to one embodiment of the disclosed systems and methods.

FIG. 4A is a perspective view of a multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 4B is a perspective cross-sectional view of a multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 4C is a perspective view of a partial multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 4D is a perspective cross-sectional view of a partial multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 4E is a perspective view of a partial multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 4F is a perspective cross-sectional view of a partial multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 5 is a cross-sectional representation of a read out integrated circuit (ROIC) showing lead metal reflector according to one embodiment of the disclosed systems and methods.

FIG. 6A is a perspective view of a multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 6B is a perspective view of a lead metal reflector according to one embodiment of the disclosed systems and methods.

FIG. 7A is a perspective view of a multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 7B is a perspective view of a lead metal reflector according to one embodiment of the disclosed systems and methods.

FIG. 8A is a perspective view of a multi-band detector element according to one embodiment of the disclosed systems and methods.

FIG. 8B is a perspective view of a lead metal reflector according to one embodiment of the disclosed systems and methods.

FIG. 9 is a simplified side cross-sectional view of a vacuum packaged focal plane array (FPA) assembly according to one embodiment of the disclosed systems and methods.

FIG. 10 is a simplified side cross-sectional view of a vacuum packaged focal plane array (FPA) assembly according to one embodiment of the disclosed systems and methods.

FIG. 11 shows a lid wafer according to one embodiment of the disclosed systems and methods.

FIG. 12 shows a tooling plate according to one embodiment of the disclosed systems and methods.

FIG. 13 is a perspective view of a wafer carrier and tooling plate according to one embodiment of the disclosed systems and methods.

FIG. 14 is a perspective view of a wafer carrier and tooling plate according to one embodiment of the disclosed systems and methods.

FIG. 15 is a block diagram of a dual-band infrared/visible imaging system according to one embodiment of the disclosed systems and methods.

FIG. 16A is a block diagram of a dual-band infrared/visible imaging system according to one embodiment of the disclosed systems and methods.

FIG. 16B is a simplified side view of an aperiodic shutter according to one embodiment of the disclosed systems and methods.

FIG. 17A is a block diagram of a dual-band infrared/visible imaging system according to one embodiment of the disclosed systems and methods.

FIG. 17B is a simplified side view of a periodic chopper according to one embodiment of the disclosed systems and methods.

FIG. 17C is a simplified side view of a periodic chopper according to one embodiment of the disclosed systems and methods.

FIG. 18 is a block diagram of dual-band sensor image fusion video processing according to one embodiment of the disclosed systems and methods.

FIG. 19 is a side view of a silicon substrate with CMOS circuitry according to one embodiment of the disclosed systems and methods.

FIG. 20 is a side view of a silicon substrate with CMOS circuitry and non-CMOS lead metal reflector layer.

DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG. 1 is a diagrammatic perspective view of an multi-band detector 10 which may be configured as a dual-band detector according to one embodiment of the disclosed systems and methods to sense visible light and thermal energy and output electrical signals representative of a two-dimensional image of that sensed visible light and/or thermal energy. In this embodiment, the multi-band detector 10 includes a multi-band focal plane array (FPA) 12 disposed on a substrate 16. The substrate 16 includes a ROIC. As will be described further herein, the ROIC may be configured to detect signals representative of visible radiation from each detector element 21 in the focal plane array 12, to integrate the thermally induced electrical signals from each detector element 21 in the focal plane array 12, and to multiplex the signals off the array with the appropriate signal conditioning and processing, e.g., as shown in FIG. 5 with signals provided to column multiplexer (column MUX) via input pad 205.

As shown in FIG. 1, an optional thermal element 17 (e.g., active heat sink) may be provided on the side of the substrate 16 opposite from the focal plane array 12, in order to serve as a form of controlled heat sink which may be used, for example, to maintain the operating temperature of integrated circuit substrate 16 within a temperature range which may be predefined. However, it will be understood that thermal element 17 does not have to be present, and that no form of temperature stabilization is required in the practice of the disclosed systems and methods.

In one exemplary embodiment, the focal plane 12 may include a plurality of dual-band detector elements 21 that are each capable of both thermal-sensing and visible light-sensing. The detector elements are arranged in a two-dimensional array, and each detector element 21 corresponds to a respective pixel in each image detected by the dual-band detector 10. In one exemplary configuration, focal plane array 12 may include 76,800 dual-band detector elements 21, which are arranged in a 320 by 240 array, although a focal plane array may be of any other size depending as needed or desired for a particular application, e.g., ranging in size from greater than or equal to an 80×60 array up to megapixel-sized arrays. For clarity, however, FIG. 1 diagrammatically depicts only about 140 detector elements. It will be recognized that the total number of detector elements 21 in the focal plane array 12 may be larger or smaller. FIG. 1 shows the detector elements 21 arranged in a two-dimensional array. Examples of two-dimensional array configurations include, but are not limited to, arrays having a shape that is rectangular, octagonal, hexagonal, circular, etc. It will be understood that detector elements may alternatively be arranged in a one-dimensional (e.g., straight or curved line of mono-pixels) array, or may be provided at arbitrary locations that do not conform to a specific pattern.

FIGS. 2-10 relate to an integrated dual-band CMOS visible imaging and microbolometer infrared imaging FPA concept as it may be implemented according to the disclosed systems and methods. One exemplary embodiment of a dual-band detector element 21 of FIG. 1 is described in more detail with respect to FIGS. 2-5. In this regard, FIGS. 2-5 illustrate a dual-band detector element 21 as it may be configured as a combination visible CMOS imager and infrared microbolometer FPA imager that incorporates a diffractive resonant cavity infrared (IR) pixel design. It will be understood that a multi-band focal plane array (FPA) assembly may be configured with as a single FPA configured to detect any two or more different bands of radiation wavelength (e.g., dual-band, tri-band, quad-band, etc.).

In the exemplary embodiment of FIGS. 2-5, an integrated dual-band FPA may be configured to simultaneously image in the visible spectrum using CMOS imager circuitry in the underlying ROIC and to image in the infrared spectrum using a suspended low thermal mass microbolometer structure. A microbolometer pixel element having dimensions of about 25 microns×about 25 microns may be fabricated using a quarter wave diffractive resonant cavity (DRC) structure which exhibits high infrared absorptance even though the suspended membrane structure is patterned into a two dimensional grid structure with a periodic grid spacing of about 5.75 microns. This results in openings in the membrane structure of about 5 microns×about 5 microns in size which are capable of transmitting visible radiation to a region in the underlying ROIC which contains CMOS circuitry. In this embodiment, visible CMOS imager circuitry may be integrated within the CMOS circuitry in the ROIC region underlying the 5 micron×5 micron openings in the membrane structure to detect visible radiation. Using such a configuration, the same dual-band pixel cell may include a 25 micron×25 micron infrared imaging pixel element and one or more 5 micron×5 micron CMOS visible-imaging diodes. It will be understood that the foregoing pixel element and membrane structure opening dimensions are used for purposes of illustration and are exemplary only. Thus, pixel elements larger than about 25 microns×about 25 microns, or smaller than about 25 microns×about 25 microns are also possible, as are membrane structure openings and corresponding CMOS visible-imaging diodes that are larger than about 5 microns×about 5 microns, or smaller than about 5 microns×about 5 microns in size.

In one embodiment of the disclosed systems and methods illustrated in FIGS. 2 and 3, a detector element 200 is shown having DRC pixel 202 that is suspended over a patterned lead metal reflector 204 in a quarterwave cavity, and the patterned lead metal reflector 204 is shown having a grating structure 206 that is the same or similar to the suspended membrane structure 208, e.g., patterned into a two dimensional grid structure with grid spacing of about 5.75 microns. Such a suspended DRC pixel structure may include a suspended silicon nitride (SiN)/amorphous silicon (a-Si)/SiN or SiN/amorphous silicon germanium (a-SiGe)/SiN membrane structure in which a thin (e.g., less than about 200 Angstroms) infrared absorbing titanium aluminum (TiAl) layer is used to enhance absorptance of infrared radiation in the thin membrane structure.

In one exemplary implementation of the embodiment of FIGS. 2 and 3, the DRC pixel membrane structure 208 may be suspended about 2 microns above the infrared reflective lead metal layer 204 that is placed over a substantially planar ROIC surface which provides for an infrared absorbing resonant cavity structure with enhanced infrared absorptance. As shown, suspended DRC pixel membrane structure 208 may be configured with a grating structure formed by openings 211 that allow for transmission of visible radiation and infrared radiation having a wavelength that is shorter than dimensional size of opening 211 through the membrane structure 208. In one embodiment of a dual-band DRC pixel design disclosed herein, the lead metal infrared reflector 204 may be optionally patterned into a grating structure similar to the suspended DRC pixel membrane 208 so as to provide for an infrared reflecting surface, but with openings 210 to allow for the transmission of visible radiation to visible spectrum photodiodes present in the visible CMOS image circuitry 504 of the unit cell ROIC 502 positioned below the lead metal infrared reflector 204, e.g., as shown in cross section for the 25 micron unit cell in FIG. 5. This is in contrast to a single band infrared DRC pixel which employs a reflective lead metal without grating openings. As shown in the Figures herein, openings 210 may be configured in one exemplary embodiment to be substantially similar in shape and size as overlying openings 211, and openings 210 may be substantially aligned with openings 211, although this is not necessary.

In one embodiment of the practice of the disclosed systems and methods, a lead metal reflector 204 may be a separate reflective layer that is placed over, or on top of, CMOS circuitry (or other circuitry such as BiCMOS circuitry, etc.) of the ROIC. However, in an alternative embodiment, the last metal level in the CMOS circuitry may be itself employed as the infrared microbolometer lead metal reflector layer 204 as shown in FIG. 19. Such an embodiment may be advantageously employed to provide a microbolometer lead metal reflector layer as part of CMOS processing, and without requiring the lead metal reflector layer to be later formed during microbolometer fabrication. Further, such an embodiment may be implemented to provide a microbolometer lead metal reflector layer for single band (infrared only) detector elements, as well as for dual-band detector elements such as described elsewhere herein. Furthermore, a single band detector element may be configured with pixel membrane and lead metal reflector structures such as illustrated in described in U.S. Pat. No. 6,777,681 and U.S. Pat. No. 6,690,014, each of which is incorporated herein by reference.

FIG. 19 shows a silicon substrate 1900 that includes CMOS circuitry layers 1910 formed thereon that are configured as individual detector element (or cells) 1960, 1962 and 1964 of an array area 1970 of a focal plane array. In the illustrated embodiment, CMOS circuitry layers 1910 include first CMOS circuit metal layer 1902, second CMOS circuit metal layer 1904, and third CMOS circuit metal layer 1906, each of which are formed during CMOS processing. Third CMOS circuit metal layer 1906 is the top (i.e., last) CMOS circuit metal layer that is at least partially exposed and, in one embodiment may be substantially completely exposed with substantially no other material formed thereon. For example, in one embodiment third CMOS circuit metal layer 1906 may be substantially completely exposed with substantially no other material formed thereon except for edge overlap of side wall passivation material disposed within opening/s 210 and moat area gap 221 formed between lead metal reflector 204 and input pad 205. In such a case a relatively small overlapping amount of such passivation material may be present on third CMOS circuit metal layer 1906 at edge/s of third CMOS circuit metal layer 1906 adjacent opening/s 210 and adjacent moat area gap 221 formed between lead metal reflector 204 and input pad 205.

As further shown in FIG. 19, CMOS circuitry layers 1910 also include first insulator layer 1903 (e.g., planarized oxide layer) between first and second CMOS circuit metal layers 1902 and 1904, and second insulator layer 1905 (e.g., planarized oxide layer) between second and third CMOS circuit metal layers 1904 and 1906, and final passivation layer 1907 (e.g., planarized oxide/nitride passivation layer) adjacent third CMOS circuit metal layer 1906. Also shown in FIG. 19 are electrically conductive metal via (plug) interconnects 1922 that are formed to extend through first insulator layer 1903 between first and second CMOS circuit metal layers 1902 and 1904, and electrically conductive metal via (plug) interconnects 1924 that are formed to extend through second insulator layer 1905 between second and third CMOS circuit metal layers 1905 and 1907. In this regard, electrically conductive metal via (plug) interconnects may be, for example, TiW, copper or any other suitable CMOS processing plug material. As indicated above, first and second insulator layers 1903 and 1905 may each be planarized silicon dioxide layers. However, any other suitable dielectric material/s may be employed for first and second insulator layers 1903 and 1905.

In FIG. 19, the last metal layer 1906 (which in this three-metal exemplary embodiment is the 3^(rd) metal in the CMOS circuitry) functions as the lead metal reflector 204 and also as the input pad 205 in the array area, and also serves as both part of the CMOS circuitry 1914 located within the array area and as part of the CMOS circuitry 1912 located outside the array area. In one exemplary embodiment, the metal layers in the CMOS circuitry may be Aluminum on an alloy of aluminum such as Aluminum Copper with a small amount of copper or Aluminum Silicon with a small amount of silicon. In such an embodiment, the aluminum or mostly aluminum alloys used in CMOS circuitry have the additional benefit of being excellent low loss reflectors of infrared radiation. In one exemplary embodiment, the last or top CMOS metal layer may be from about 0.25 micron to about 1 micron thick and may be applied using any suitable processing method, e.g., sputtering, etc. In another exemplary embodiment, electrically conductive metal via (plug) interconnect 1924 may be of a different material (e.g., at least one of TiW or copper) than a material (e.g., at least one of aluminum, aluminum copper or aluminum silicon) of at least partially exposed top metal layer 1906. In another exemplary embodiment, electrically conductive metal via (plug) interconnect 1924 may be formed during a different processing step than is top metal layer 1906, and/or electrically conductive metal via (plug) interconnect 1924 may be formed at a different time during processing than is top metal layer 1906.

In one exemplary embodiment of FIG. 19, the last metal layer 1906 in the CMOS circuitry may be used as the lead metal reflector in a manner that may be employed to result in excellent surface planarity. Using CMOS processing, an oxide layer (1903 or 1905) planarized using Chemical Mechanical Polishing (CMP) may be placed between metal layers 1902 and 1904, and between metal layers 1904 and 1906, together with metal via interconnects 1922 and 1924 as previously described. Also, after the last CMOS metal, an oxide/nitride passivation layer 1907 (e.g., which may be made the same thickness as the last metal layer of CMOS circuitry) may be deposited to passivate the etched metal sidewalls. As shown in FIG. 19, the resulting structure of this exemplary embodiment has an exposed upper surface 1950 that is substantially planar across the array area 1970. Further, exposed upper surface of top metal layer 1906 is substantially planar across each detector element (cell) 1960, 1962 and 1964 as shown. A planar surface is advantageous for fabrication of a microbolometer structure due to the fact that at linear pixel dimensions of about 30 microns or less, the width of the thermal isolation legs may be about 1 micron or less. When working with such structural dimensions, a planar surface helps to ensure, among other things, faithful printing of about 1 micron (or narrower) wide legs in a photolithographic resist coat, expose and develop process.

In a further exemplary embodiment, upper surface 1950 of FIG. 19 may be characterized as being substantially planar and substantially continuous in those areas of array area 1970 that are disposed between moat areas 221 and between any opening/s 210 that may be present in upper surface 1950, and in a further exemplary embodiment may be characterized as being substantially planar and substantially continuous across each detector element (cell) 1960, 1962 and 1964 between moat areas 221 and opening/s 210 of these cells. For example, FIG. 7B illustrates an embodiment in which an upper surface 201 of lead metal reflector 204 is substantially planar across a detector element (cell), and is substantially continuous across the detector element except at moat area 221. In another example, FIGS. 2B and 6B illustrate embodiments in which an upper surface 201 of lead metal reflector 204 is substantially planar across a detector element (cell), and is substantially continuous across the detector element except at moat area 221 and opening/s 210.

The embodiment of FIG. 19 may be implemented to provide a CMOS lead metal reflector layer and structure that is in contrast to the conventional structure of FIG. 20 in which portions 2010 of non-CMOS lead metal reflector layer 2014 are formed on sidewalls of input via structures 2016 and on top of top metal layer 2006 (i.e., to provide direct connection to metal of input pads 2050) so that the resulting non-CMOS lead metal reflector layer 2014 is non-planar at the location of the input via areas and is consequently not substantially planar across an array area of a focal plane array of detector elements. Further, the exemplary embodiment of FIG. 19 employs a lead metal reflector layer that is the same as top CMOS metal layer 1906 and that does not make intimate physical contact with any other metal layer, but instead is connected to other underlying CMOS layers by separately formed electrically conductive via interconnects. This is in further contrast to the conventional structure of FIG. 20 where the same metal of non-CMOS lead metal reflector layer 2014 is formed within input via structures 2016 so that non-CMOS lead metal reflector layer 2014 makes intimate physical contact with top CMOS metal layer 1906 and interconnect layers 2004 and 1906.

As shown in FIGS. 2-4, narrow-width (e.g., leg width of less than or equal to about 1 micron) legs 220 are each wrapped around two sides of the DRC pixel 202 to provide for high thermal isolation for the pixel. In one exemplary pixel structures may have linear dimensions of about 30 microns or less (i.e., the periodic spacing from cell to cell). However, linear dimensions of greater than about 30 microns are also possible.

As illustrated in the exemplary embodiment of FIGS. 2-4, each of the thermal isolation legs 220 of a multi-band detector element 200 may have an upper surface 222, the substantial entirety of which is substantially planar and oriented in substantially parallel relationship to the major plane of a corresponding suspended membrane 208. In one exemplary embodiment, each of the thermal isolation legs 220 of a multi-band detector may be oriented in substantial parallel and substantially coplanar relationship to the substantially planar upper surface 209 of a corresponding suspended membrane 208 of the detector. As so configured and shown in FIGS. 2 and 4A, the upper surface 222 of a first end 203 of each thermal isolation leg 220 (i.e., end located proximal to the membrane 208 and attached or otherwise contiguous the upper surface 209 of the membrane 208) may be configured to lie in the same plane as the upper surface 222 of the opposite second end 207 of the thermal isolation leg 220 (e.g., opposite end located distal to the membrane 208 and attached or otherwise contiguous with an interconnect 302 to underlying ROIC circuitry). As illustrated, such a substantially planar thermal isolation leg structure may be advantageously configured for interconnection with underlying ROIC circuitry without stepping-down or ramping downward to the lead metal reflector 204 and/or substrate underneath (e.g., by using a separate interconnect structure/s such as a TiW interconnect/SiN capping structure combination, or using a TiW interconnect structure alone, to couple the end of the substantially planar leg to the lead metal or substrate). In the practice of the disclosed systems and method, each of the legs 220 of a DRC pixel 202 may additionally or alternatively be characterized as being oriented in substantially parallel relationship with a substantially planar upper surface 201 of a corresponding lead metal reflector 204.

FIG. 4A shows a completed DRC pixel structure of multi-band detector element 200 having capping nitride (SiN) top layer 301, and FIG. 4B shows this structure in cross section. FIG. 4C shows DRC pixel structure of multi-band detector element 200 minus the capping SiN layer to expose titanium aluminum (TiAl) electrode absorber layers 304 and 306 and titanium tungsten (TiW) tab metal interconnect 302 formed above and connecting to input pad 205. FIG. 4D shows the structure of 4C in cross section. FIG. 4E shows DRC pixel structure of multi-band detector element 200 minus the capping SiN layer, TiAl electrode absorber, and TiW tab metal interconnect to expose patterned mid-SiN layer 320 formed over a layer 322 of amorphous silicon (a-Si) or amorphous silicon germanium (a-SiGe) that itself is formed over a first (bottom) SiN layer 324. FIG. 4F shows the structure of FIG. 4E in cross section.

As shown in FIG. 4C TiW tab metal interconnect 302 and TiAl electrode absorber 306 are provided to connect a distal end 207 (e.g., in this exemplary case the distal end 207 of the leg 220 is provided with a square terminal leg opening) of each leg 220 to ROIC circuitry 502 (e.g., see FIG. 5) and lead metal reflector structure 204. Advantageously, such a substantially planar leg configuration may be provided to increase process accuracy, especially for fabrication of structures having smaller geometries. Tighter depth of focus control in photolithographic printing becomes more important in faithfully printing smaller geometries, as does the process ability to remove areas of thicker photoresist in non-planar regions when exposure conditions are tightly controlled. In this regard, substantially planar leg configurations maybe employed in one embodiment to increase focus accuracy of photolithographic processes when fabricating legs of less than or equal to about 1 micron in width.

As shown in FIG. 5, the suspended planar DRC pixel 202 may be connected to the CMOS read out integrated circuit (Si ROIC) 502 which may include a CMOS infrared switched capacitor integrating amplifier circuit 506 per each unit cell for each pixel 202 to integrate infrared bolometer signal. As shown in FIG. 5, infrared switched capacitor integrating amplifier circuit 506 may be coupled to input pad 205 via an input field effect transistor (FET) and may be provided with a reset switch coupled for purposes of resetting the sampling circuit. Infrared switched capacitor integrating amplifier circuit 506 may also include integrating capacitor C2, transfer capacitor C3, and averaging capacitor C4 coupled as shown with switches PS1 and PS2 therebetween. Also shown is an output provided by circuitry 506 for a column by column multiplexer circuit to readout the infrared signal output via IR signal pixel read switch. FIG. 5 also shows how visible photodiodes of unit cell visible CMOS imager circuitry 504 may be positioned to receive visible spectrum radiation transmitted through openings 210 and to provide output signals for a column by column multiplexer circuit to readout the visible image signal and visible signal pixel read switch components. As shown, visible CMOS imager circuitry 504 also includes a reset switch component for purposes of resetting the input nodes.

Referring again to FIG. 2, the connection from the end of the long planar thermal isolation leg 220 (e.g., each leg having two perpendicular leg segments that are each about 20 microns in length for a total leg length of about 40 microns per leg) and the lead metal reflector 204 placed on top of the CMOS ROIC in each unit cell may be made in one embodiment by a Titanium-Tungsten (TiW) tab metal interconnect 302 of about 1750 Angstroms, although other configurations and dimensions are possible. The unit cell lead metal reflector 204 shown in FIG. 2 is shown provided with an input pad 205 which connects to the input of the CMOS ROIC integrating amplifier 506 of FIG. 5. In this embodiment, the large reflective area of the lead metal 204 in FIG. 2 may be connected to the detector common bias in the ROIC which allows the pixel 202 to be biased up to a voltage of about 1 to about 3 volts.

Various views and cross sections of one exemplary embodiment of DRC pixel structure are shown in FIGS. 2 through 4. The suspended membrane portion 208 of the DRC pixel 202, the amorphous silicon (a-Si) or amorphous silicon germanium (a-SiGe) layer 322 with a temperature dependent resistance may be sandwiched between the first SiN and mid-SiN layers 324 and 320, respectively. Contact windows may be patterned into the mid-SiN layer 320 to expose the a-Si or a-SiGe prior to the deposition of a thin TiAl layer 306. The TiAl layer 306 is subsequently patterned into the electrode absorber element. It is noted that the thin TiAl electrodes contribute to infrared absorptance thereby making the entire body and surface of the arms of the pixel 202 infrared absorbing. The patterned electrode/absorber may be covered with a capping layer 301 of SiN. The cap SiN layer 301 may be provided to not only passivate the TiAl metal, but also to provide additional stiffness to manage stress and maintain a planar, structurally robust suspended pixel element 202. In one embodiment illustrated herein, a thermal isolation leg 220 may have the same thickness and/or layer structure as the corresponding membrane 200 of the same pixel 202. However, it is also possible that the leg may be fabricated to have a different layer structure and/or thickness than the corresponding membrane of the same pixel.

The layer thicknesses and leg widths may vary depending on the size of the pixel 202. For example, a 25 micron×25 micron pixel 202 may have a first (bottom) SiN layer 324 of about 300 angstroms thick; an a-Si or a-SiGe layer 322 of about 600 angstroms thick; a middle SiN layer 320 of about 400 angstroms thick; and a capping SiN layer 301 of about 1000 angstroms thick; and may have a leg width of from about 0.5 microns to about 1 microns, it being understood that the forgoing width and thickness values are exemplary only. In one exemplary embodiment, the patterned suspended membrane 208 in the DRC pixel 202 exhibits high infrared absorptance (greater than about 80%) across the 8 to 12 micron long wave infrared spectral band. DRC pixel structures of the disclosed systems and methods may also exhibit high infrared absorptance (greater than about 80%) across the 3 to 5 micron mid wave infrared spectral band as well. Further information on detector elements or pixels having a diffractive resonant cavity may be found in U.S. Pat. No. 6,777,681, which is incorporated herein by reference.

In one exemplary embodiment, allocation of real estate in a 25 micron×25 micron unit cell such as illustrated in FIG. 5 may be as follows: the CMOS circuitry 506 for the infrared microbolometer may be configured to require about 289 microns squared, leaving as much as about 336 microns squared for the visible photodiode(s) and CMOS circuitry 504.

FIG. 6A and 6B illustrate an alternative and exemplary embodiment of multi-band detector configured as a dual-band detector element 200 having a DRC microbolometer pixel (e.g., quarterwave cavity) design. In this embodiment, the dual-band detector element 200 includes a continuous solid membrane structure 208 that has a single opening 211 provided in the suspended membrane 208 directly over a single opening 210 provided in the lead metal reflector 204, and over active visible imaging circuitry. Single opening 210 provided in lead metal reflector 204 is shown in further detail in FIG. 6B. In the illustrated exemplary embodiment of FIGS. 6A and 6B, the openings 211 and 210 in both the suspended membrane 208 and the lead metal reflector 204 are square in shape with side dimensions of about 5 microns×about 5 microns, and are positioned in substantial optical alignment with each other so that visible spectrum radiation is transmitted.

It will be understood, however, that membrane and lead metal reflector openings (or openings within any other type of underlying detector structure) of any other combination of shape, size and/or which are at least partial aligned, may be employed that are suitable for allowing visible energy to pass through to underlying visible imaging circuitry It will also be understood that it is not necessary for the number and/or size of openings in a membrane to be the same as the number and/or size of openings provided in a corresponding lead metal reflector or other underlying detector structure. For example, FIG. 8A shows another exemplary embodiment of a dual-band detector element 200 having a DRC microbolometer pixel (e.g., quarterwave cavity) design, and having a single opening 210 provided in the lead metal reflector 204 that underlies multiple grid openings 211 provided in the microbolometer membrane 208 (e.g., similar to the membrane grid of FIGS. 2-4). Single opening 210 provided in lead metal reflector 204 is shown in further detail in FIG. 8B. In the illustrated exemplary embodiment of FIGS. 8A and 8B, the detector components are configured so that visible spectrum radiation is transmitted through at least one of the membrane grid openings 211 and through the single opening 210 in the lead metal reflector 204 to underlying visible-imaging circuitry.

FIG. 7A illustrates another exemplary embodiment in which each of the thermal isolation legs 220 of an infrared detector element 200 may have an upper surface 222, the substantial entirety of which is substantially planar and oriented in substantially parallel relationship to the major plane of a corresponding suspended membrane 208 that has no openings defined therein, e.g., as in the case of a single-band infrared detector element. In one exemplary embodiment, each of the thermal isolation legs 220 of a single-band detector may be oriented in substantial parallel and substantially coplanar relationship to the substantially planar upper surface 209 of a corresponding suspended membrane 208 of the detector. As so configured, the upper surface 222 of a first end 203 of each thermal isolation leg 220 (i.e., end located proximal to the membrane 208 and attached or otherwise contiguous with the upper surface 209 of the membrane 208) may be configured to lie in the same plane as the upper surface 222 of the opposite second end 207 of the thermal isolation leg 220 (e.g., opposite end located distal to the membrane 208 and attached or otherwise contiguous with an interconnect 302 to underlying ROIC circuitry). As illustrated, such a substantially planar thermal isolation leg structure 220 may be advantageously configured for interconnection with underlying ROIC circuitry without stepping-down or ramping downward to the lead metal reflector and/or substrate underneath (e.g., by using a separate interconnect structure/s such as a TiW interconnect/SiN capping structure combination, or using a TiW interconnect structure alone, to couple the end of the substantially planar leg to the lead metal or substrate). In the practice of the disclosed systems and method, each of the legs 220 of a single-band DRC pixel 202 may additionally or alternatively be characterized as being oriented in substantially parallel relationship with a substantially planar upper surface 201 of a corresponding lead metal reflector.

The disclosed single-band and multi-band focal plane arrays and systems thereof may be fabricated using any methodology and/or materials (e.g., wafer-level packaging, single die-level packaging, etc.) that is suitable for providing a FPA and/or system having capabilities and characteristics as described elsewhere herein. For example, in one embodiment, a dual-band uncooled integrated infrared and visible CMOS imager FPA may be vacuum packaged, e.g., using wafer level vacuum packaging. Vacuum packaging may be employed in such an embodiment to achieve good thermal isolation for high sensitivity uncooled microbolometer array performance. Further information on vacuum packaging of focal plane arrays may be found in U.S. Pat. No. 6,586,831, U.S. Pat. No. 6,521,477, U.S. Pat. No. 6,479,320, United States Patent Publication number 2004/0219704, and U.S. patent application Ser. No. 11/141,356, each of which is incorporated herein by reference.

Two exemplary embodiments of a wafer-level packaged dual-band FPA are shown in FIGS. 9 and 10. FIG. 9 illustrates a cross sectional view of a wafer-level vacuum packaged dual-band (M×N) FPA 900 having a visible/infrared transparent lid 902 with an etched cavity 904, and FIG. 10 illustrates a cross sectional view of a wafer-level vacuum packaged dual-band (M×N) FPA 1000 having a planar visible/infrared transparent lid 1002 without etched cavity. Each of visible/infrared transparent lids 902 and 1002 may be materials such as ZnSe or other suitable material that is transmissive in both visible spectrum and infrared spectrum (e.g., sapphire materials, zinc sulfide materials, etc.). As shown in FIG. 9, a dual band FPA 912 is provided on a imager device wafer substrate 916 that may also include, for example, ROIC/CMOS 502 of FIG. 5. Similarly, FIG. 10 shows a dual band FPA 1012 disposed on a imager device wafer substrate 1016 that may include, for example ROIC/CMOS 502 of FIG. 5. Each of dual band FPA 912 and 1012 may be a M×N FPA with suspended thermally isolated infrared absorbing detector pixel elements. Antireflection surfaces 918 (e.g., visible/IR antireflection coatings) may be provided on inner and outer surfaces 950 and 960 of visible/infrared transparent lid 902 over FPA 912 as shown in FIG. 9. Similar antireflection surfaces 1018 may also be provided on inner and outer surfaces 1050 and 1060 of visible/infrared transparent lid 1002 over FPA 1012 as shown in FIG. 10.

FIG. 9 also shows infrared optically blocked reference pixel array 908 (i.e., array 908 of P×Q reference pixel elements) that is disposed on the substrate of wafer 916 as shown. An optically blocking structure in the form of a gold/platinum/titanium (Au/Pt/Ti) metallization blocking layer 906 is shown fabricated on the inner surface of the lid wafer element 902 directly over the reference row 108. A blocking layer may be so configured and positioned to at least partially or completely block infrared radiation from reaching reference pixel array 908. Similarly, FIG. 10 shows infrared optically blocked reference pixel array 1008 (i.e., array 1008 of P×Q reference pixel elements) that is disposed on the substrate of wafer 1016 as shown. An optically blocking structure in the form of a gold/platinum/titanium (Au/Pt/Ti) metallization blocking layer 1006 is shown fabricated on the inner surface of the lid wafer element 1002 directly over the reference row 1008 to at least partially or completely block infrared radiation from reaching reference pixel array 1008. Further information on optically blocked reference pixel arrays may be found in U.S. patent application Ser. No. 11/141,361, which is incorporated herein by reference.

As further shown in FIG. 9, a gold-tin (AuSn) solder seal 920 is shown disposed between gold-platinum-titanium metallization layers 922 provided on each of the bond surfaces of lid 902 and FPA/ROIC device wafer substrate 916, i.e., as a peripheral seal around FPA 912 and reference array 908. Similarly, in FIG. 10, a gold-tin (AuSn) solder seal 1020 is shown disposed between gold-platinum-titanium metallization layers 1022 provided on each of the bond surfaces of lid 1002 and FPA/ROIC device wafer substrate 1016, i.e., as a peripheral seal around FPA 1012 and reference array 1008. Further information on such vacuum-packaging methodology may be found in U.S. patent application Ser. No. 11/141,356, which is incorporated herein by reference. However, any other suitable methodology for forming a vacuum tight peripheral seal around FPA 912 or 1012 and respective reference array 908 or 1008 may be employed, e.g., such as lid and device sealing rings and heat activated solder layer and non-heat activated sealing layers described in U.S. Pat. Nos. 6,586,831, 6,521,477 and 6,479,320, each of which are incorporated herein by reference.

It will be understood that a multi-band (e.g., dual-band) FPA may alternatively be packaged at the single die-level, e.g., using ceramic package with optical window of ZnSe or other suitable material that is transmissive in both visible spectrum and infrared spectrum (e.g., sapphire materials, zinc sulfide materials, etc.). It is further understood that the window materials may be coated with anti-reflection coatings designed for each material, which simultaneously enhance the transmission in all the spectral bands of interest, e.g., visible, near IR, midwave IR, and long wave IR.

In one embodiment of the disclosed systems and methods, two wafer materials, in the form of a first segmented wafer and a second unsegmented wafer having different TCEs, may be bonded together, with or without the presence of a vacuum in the final package. In this embodiment, a first one of the wafers may be first segmented (e.g., reticulated and diced up) into multiple portions (e.g., individual die-sized parts) so that difference in material expansion characteristics due to the difference in TCEs between the two different wafer materials of the first and second wafers is limited to the relatively smaller dimensions of each portion of the segmented wafer (e.g., limited to each die) rather than to the relatively larger dimensions of the original unsegmented first wafer.

Once segmented, the individual portions (e.g., segmented window lid components) of the segmented first wafer may be held in relative alignment with corresponding components (e.g., individual device die) on the unsegmented second wafer so that mating surfaces of all of the segmented first wafer portions may be bonded simultaneously to corresponding mating surfaces of the unsegmented second wafer. Individual portions of the segmented first wafer may held in alignment with corresponding components of the unsegmented second wafer in any suitable manner, e.g., by using spacer structures such as a grid of spacer wires or thin spacer walls that form compartments for retaining the segmented portions, by temporarily adhering a non-mating surface of the segmented portions of the first wafer to a substantially planar surface so that the mating surface of the segmented portions are held in position for simultaneously mating with the mating surface of the unsegmented components of the second wafer, etc.

Using the disclosed systems and methods, many types of non-silicon-based materials (e.g., materials that are optically transmissive in the visible spectrum) may be bonded to silicon-based materials (e.g., a silicon wafer), with or without the presence of a vacuum in the final package. Specific examples of MEMS devices that may be packaged in this embodiment include, but are not limited to, optical devices such as single-band or multi-band detector FPAs, reflective displays such as digital micromirror device (DMD) elements of a digital light processing (DLP) system, resonant reflective devices for choppers & scanners, optical input/output (I/O) devices, devices for optical communication, etc. Specific examples of FPA devices include, but are not limited to, single-band or multi-band integrated FPAs (e.g., single band visible FPA devices, or integrated dual-band FPA devices that are capable of detecting both near IR spectrum radiation and visible spectrum radiation), and optically sensitive cantilever devices. Examples of non-silicon-based materials that are optically transmissive in both the visible spectrum and the IR spectrum include, but are not limited to, zinc selenide materials, sapphire materials, zinc sulfide materials, etc. Such materials may be employed in the practice of the disclosed systems and methods as lid wafer materials for packaging or vacuum-packaging multi-band integrated FPA devices that are capable of detecting both IR spectrum radiation and visible spectrum radiation.

FIG. 11 shows a lid wafer 1100 as it may be patterned (e.g., with solder base metal) and then segmented (e.g., reticulated and diced-up) according to one exemplary embodiment as indicated by dashed lines in FIG. 11 to form individual window lid components 1120. In this regard, the mating surface of the individual window lid components of the segmented first wafer may be patterned with a solder base metal seal ring and solder (e.g., perform or deposited or plated solder) such as shown in FIGS. 9 and 10, segmented, and then placed into compartments of a tooling plate 1200 of FIG. 12 in a manner as described further herein.

In the exemplary embodiment of FIG. 11, lid wafer 1100 may be a non-silicon-based material (e.g., zinc selenide material, sapphire material, zinc sulfide material, etc.) that is optically transmissive in both the visible spectrum and the IR spectrum, or may be any other type of wafer material (optically transmissive or non-optically transmissive) that is suitable for segmentation into individual components that are to be bonded to a separate wafer, e.g., a wafer of material that is dissimilar to window lid components 1120, and that has a TCE that is substantially different from the TCE of the material of window lid components 1120. In one embodiment, window lid components 1120 may be each configured in the form of visible/infrared transparent lids such as illustrated in FIGS. 9 (with etched cavity) and FIG. 10 (planar).

FIG. 12 shows a lid component tooling plate 1200 as it may be configured and employed in one exemplary embodiment to hold individual segmented window lid components 1120 of FIG. 11 in place in alignment for simultaneous mating with individual device die of a device wafer. As shown, tooling plate 1200 includes a plurality of spacer structures 1240 configured as a grid on tooling plate substrate 1230 (e.g., a carrier substrate polished flat to less than about 5 microns or other suitable substrate) of tooling plate 1200. In the illustrated embodiment, spacers 1240 include a plurality of spacer wires having opposite ends that are secured around the periphery of substrate 1230 at right angles so as to form a grid of individual compartments 1220 dimensioned to be suitable for containing individual segmented window lid components of lid wafer 1100 as shown. When spacer structures are so employed for containing segmented components, dimensions of the window lid components may be fabricated to be complementary (e.g., to accept or allow for) the outer dimensions of the spacer structures (e.g., outer diameter of the spacer wires). This may be done, for example, by fabricating the window lid components 1120 such that the width of each component 1120 plus the diameter of spacer wire 1240 is equal to the center-to-center distance of device die 1320 (see FIG. 13) in both x and y dimensions. In one exemplary embodiment, diameter of spacer wire 1240 may be from about 4 to about 10 mils, although greater or lesser diameters are possible. Also shown in FIG. 12 are optional edge guide bars 1210 that may be provided in this embodiment for the purpose of ensuring parallelism of spacer wires 240. Edge guide bars 1210 are optional and may or may not be used.

In one embodiment of the disclosed systems and methods, each of tooling plate 1300, tooling plate 1200, spacer structures 1240 and optional edge guide bars 1210 may be manufactured of the same material (e.g., inconel, graphite, molybdenum, stainless steel, etc.), or may be otherwise manufactured of materials having similar thermal expansion characteristics.

As shown in FIG. 13, individual window lid components 1120 are held in place within compartments 1220 of tooling plate 1200. The number of window lid components 1120 may be of equal or different number (e.g., greater or lesser number) than the number of device die 1320. Lid component tooling plate 1200, in turn, is positioned adjacent device tooling plate (e.g., wafer carrier, device wafer carrier, ROIC wafer carrier) 1300 that holds or retains device wafer 1310 thereon. Wafer alignment guide structures are shown provided in this exemplary embodiment in the form of guide pins 1340 that extend upwardly from tooling plate 1200, and that are configured to be received in guide pin openings 1350 defined within tooling plate 1300 as shown. In this exemplary embodiment, guide pins 1340 and guide pin openings 1350 are positioned so that individual window lid components 1120 are in alignment with individual device die 1320 of device wafer 1310 when guide pins 1340 are received within guide pin openings 1350 in tooling plate 1200. Once so aligned, individual window lid components 1120 are in alignment with respective individual device die 1320 to which they are to be bonded, and tooling plate 1200 may be brought together with wafer carrier 1200 to simultaneously assemble all of window lid components 1120 to device dice 1320. In one embodiment, tooling plate 1200 holding individual (e.g., segmented) window lid components 1120 may be oriented to be on the lowermost tooling plate (underneath device tooling plate 1300) so that force of gravity acts to hold the individual components within their respective compartments 1220.

After tooling plate 1200 is brought together with tooling plate 1300 as shown by arrows in FIG. 14, individual window lid components 1120 may be bonded to respective individual device die 1320, e.g., sealed and optionally vacuum packaged using any suitable methodology. Bonding may be performed using, for example, a suitable solder such as described elsewhere herein, or alternatively may be performed using any other type of suitable bonding material. For example, where thermal expansion coefficients of device die and window lid component materials are sufficiently similar (e.g., Pyrex glass window lid component bonded to silicon device die) such materials may be bonded anodically. In another embodiment bonding may be performed using organic materials such as epoxy where hermeticity requirements are relaxed, etc.). Advantageously, since individual window lid components have been segmented from lid wafer 1100, the effect of any difference in thermal expansion between lid wafer material and device wafer material for a given individual component is limited to the relatively small window lid component dimensions rather than the relatively large lid wafer dimensions. After bonding, device wafer 1310 now has an array of segmented window lid components 1120 covering all die sites 1320 in this embodiment, although it is also possible in another embodiment that only a portion of die sites 1320 may be covered. Device wafer 1310 may then be segmented (e.g., sawed) into individual completed die such as shown in FIGS. 9 and 10.

When soldering is employed to bond individual window lid components 1120 to respective individual device die 1320 of device wafer 1310, any heating and assembly methodology may be employed that is suitable for bonding individual window lid components 1120 to respective individual device die 1320 using solder. For example, device wafer 1310 and individual window lid components 1120 with solder may be heated prior to bringing tooling plate 1200 together with wafer carrier 1200 to accomplish bonding of window lid components 1120 to device dice 1320. Alternatively, tooling plate 1200 and wafer carrier 1200 may be brought together first, followed by heating of device wafer 1310 and individual window lid components 1120 to accomplish bonding of window lid components 1120 to device dice 1320. Although solder may be patterned, deposited or otherwise placed on individual lid components and/or device die in any suitable manner for bonding, in one embodiment solder may be placed on lid component/s or device die that are contained on the lowermost tooling plate (oriented underneath the other tooling plate) so as to take advantage of gravity effects.

In another embodiment of the disclosed systems and methods, it is possible that not all compartments 1220 of tooling plate 1200 are filled with window lid components 1120 (i.e., so that some of compartments 1220 remain empty) prior to bringing tooling plate 1200 together with wafer carrier 1200 so as to accomplish bonding of window lid components 1120 to only a portion of device dice 1320 of device wafer 1310. Such an embodiment may be desirable, for example, to conserve window lid components in a case where some device die 1320 are defective and it is therefore not desired to package all die 1320 of wafer 1310.

In another embodiment of the disclosed systems and methods, it is possible that not all compartments 1220 of tooling plate 1200 are filled with the same type of components for assembly and bonding to device dice 1320 of tooling plate 1200. For example, a first portion of the compartments 1220 of tooling plate 1200 may be filled with window lid components 1120 of one type of material (e.g., zinc selenide material), and a second portion of the compartments of 1220 of tooling plate 1200 may be filled with window lid components 1120 of another different type of material (e.g., sapphire material) so as to accomplish simultaneous bonding of two different types of window lid components 1120 to device dice 1320 of device wafer 1310. Similarly, it is also possible that three or more different types of window lid components 1120 may be placed in three or more corresponding portions of the compartments of 1220 of tooling plate 1200 so as to accomplish simultaneous bonding of three or more different types of window lid components 1120 to device dice 1320 of device wafer 1310.

Besides different types of window lid components 1120, it is also possible that a portion of compartments of 1220 of tooling plate 1200 may be filled with a first type of components (e.g., window lid components 1120), while one or more other portions of compartments 1220 are filled with one or more other different types of components (e.g., one or more types of non-window lid components) so as to accomplish simultaneous bonding of the first type of components and one or more other types of components to device dice 1320 of device wafer 1310.

FIGS. 15 through 17 show block diagrams of three embodiments of dual-band visible/infrared imaging systems as they may be provided using the disclosed systems and methods. In the illustrated embodiments, visible and infrared radiation 1508 radiating from the scene is incident on visible/infrared-transmitting optics 1510, for example, zinc selenide (ZnSe) optics. However, reflective optics may be alternatively employed. As shown in each of FIGS. 15-17, the visible and infrared radiation is focused by the optics 1510 onto a dual-band infrared FPA/CMOS Imager 1512 (e.g., wafer level packaged dual-band uncooled infrared FPA and visible CMOS imager array), which is provided in each of the illustrated embodiments as a wafer-leveled packaged dual-band uncooled integrated infrared FPA and visible CMOS imager array.

As shown in the embodiment of FIGS. 15-17, dual-band infrared FPA/CMOS Imager 1512 provides a multiplexed visible CMOS imager array output 1520 to visible spectrum signal processing electronics 1522 which, in turn, provides a processed visible image signal 1524 to image fusion signal processing electronics 1540. Likewise, dual-band infrared FPA/CMOS Imager 1512 provides a multiplexed infrared FPA output 1526 to infrared spectrum signal processing electronics 1528 which, in turn, provides a processed infrared image signal 1530 to image fusion signal processing electronics 1540. Image fusion signal processing electronics 1540 produces a fused infrared/visible image signal 1542 that in this case is provided to video output display 1544. Further information regarding image fusion signal processing is described herein in relation to FIG. 18.

In the exemplary embodiment of FIG. 15, a dual-band infrared/visible imaging system 1500 is illustrated without having a chopper or shutter in the optical train between the source of radiation and the dual-band infrared FPA/CMOS Imager 1512. However, as shown in the exemplary embodiments of FIGS. 16 and 17, a shutter and/or chopper may be provided to at least partially correct drift in infrared FPA offsets. As shown, such a shutter and/or chopper may be placed in the optical train between a source of radiation 1508 and a dual-band infrared FPA/CMOS Imager 1512 and, in the illustrated examples, is shown placed between optics 1510 and dual-band infrared FPA/CMOS Imager 1512.

In the embodiment illustrated in FIG. 16A, a dual-band infrared/visible imaging system 1600 may be provided having an opaque aperiodic shutter 1602 placed in front of the dual-band infrared FPA/CMOS Imager 1512 in the optical train between a source of radiation 1508 and the dual-band infrared FPA/CMOS Imager 1512 to calibrate out any spatial pattern noise in the multiplexed infrared FPA output 1526 which may be induced by either temperature drift or 1/f noise. The shutter is inserted as needed into the optical train to block the incident radiation and to provide an isothermal surface with which the output of the dual-band infrared FPA/CMOS Imager 1512 may be recalibrated. FIG. 16B is a simplified side view of aperiodic shutter 1602, in this exemplary embodiment provided with a mast 1604 that is mechanically coupled to at least partially rotate around a point 1606 so that shutter 1602 may be selectably inserted and removed from the optical train in the direction of the double-headed arrows.

In the embodiment illustrated in FIG. 17A, a dual-band infrared/visible imaging system 1700 may be provided having a periodic rotating chopper 1702 (opaque or diffusing periodic chopper) may be placed in front of the dual-band infrared FPA/CMOS Imager 1512 in the optical train between a source of radiation 1508 and the dual-band infrared FPA/CMOS Imager 1512 to calibrate out any fixed pattern noise in the multiplexed infrared FPA output 1526 every frame. For example, if the imager 1512 is running at a 30 Hz frame rate, then the chopper 1702 may be configured to rotate to block (i.e., in the case of an opaque chopper) or diffuse (i.e., in the case of a diffusing chopper) the incident radiation every frame for half of the frame time. The output from the blocked or diffused half frame is subtracted from the output from the “open” half frame thereby removing any temperature drift-induced or 1/f noise induced spatial pattern noise in the multiplexed infrared FPA output 1526.

FIG. 17B is a simplified side view of periodic rotating chopper 1702 that is configure to rotate around a center point 1704 in either clockwise or counter clockwise direction so that chopper blades 1706 a and 1706 b are each periodically inserted and removed from the optical train. In such an embodiment, chopper portions 1708 a and 1708 b may each be “open” to pass incident radiation. As shown in FIG. 17B, chopper portions 1708 a and 1708 b may be disposed between blades 1706 a and 1706 b, each of which may each be opaque or diffusing in a manner as described above. Further information on choppers may be found in U.S. Pat. No. 4,143,269; U.S. Pat. No. 5,021,663; U.S. Pat. No. 5,051,591; U.S. Pat. No. 5,952,661; U.S. Pat. No. 5,965,890; U.S. Pat. No. 6,034,371; U.S. Pat. No. 6,232,044; U.S. Pat. No. 6,437,332; and U.S. Pat. No. 7,102,832, each of the foregoing United States patents being incorporated herein by reference.

It will be understood that provision of an aperiodic shutter and/or periodic chopper is optional, and that in one embodiment no aperiodic shutter and/or no periodic chopper may be positioned between a source of radiation and a FPA, e.g., as shown in FIG. 15.

FIG. 18 is a block diagram illustrating dual-band sensor image fusion video processing 1800 as it may be implemented using one embodiment of the disclosed systems and methods. In this embodiment, sensor data 1802 for each band (IR band 1802 a and visible band 1802 b) is received and if the resolution of the images is different, then the resolution may be matched in block 1804 by resizing the lower resolution image as needed to match the higher resolution image. However, since some fusion algorithms provide for differences in spatial resolution this resizing may not be necessary. Images may then be optionally expanded or compressed in dynamic range to better match the dynamic range requirements of the fusion algorithm/s of block 1808. This image expansion/compression of block 1806 may be, for example, a linear or a non-linear transform. Image fusion of visible and IR images may be accomplished in block 1808 using any algorithm suitable for fusing multiple (e.g., two) images. Examples of such image fusion algorithms include, but are not limited to, image fusion algorithms ranging from simple addition to complicated mathematical algorithms or neural networks. Specific examples of fusion algorithms suitable for the fusion of infrared and visible spectrums include, but are not limited to, multiscale decomposition-based algorithms such as Laplacian (LAP) pyramid, shift invariant discrete wavelet transform (SiDWT) and the filter-subtract-decimate (FSD) pyramid. Exemplary fusion algorithms may result in monochrome or color representations of the fused image as image data 1810, although other representations are possible. The data is then formatted for display in block 1812 and output as video data 1814 for display.

In one embodiment of the disclosed systems and methods, a multi-band detector for a multi-band integrated FPA may be provided with color imaging capability in the UV-VISIBLE spectral band. In such an embodiment, color imaging may be obtained by providing a color filter over each pixel of the Visible detector array in a path of visible spectrum radiation between said one or more openings in an infrared detector membrane and each pixel element. Such color filter arrays may be provided, for example, by deposition of interference multilayer coatings designed to transmit in the Red, Green, or Blue spectral bands, or any other band of interest. One example of such a multilayer coating configuration includes alternating layers of silicon dioxide or silicon nitride (low index of refraction) and amorphous silicon (high index of refraction), although any other coating configuration suitable for providing a color filter array may be employed. In such an embodiment, visible array pixels and associated color filters may be placed under a opening of the microbolometer pixels, so that one or more visible response pixels may be housed under each infrared pixel.

In another embodiment, a multi-band FPA may be provided with color correction within the infrared spectrum. Color correction may be useful or needed for a multi-band FPA system where optical elements (e.g., lenses, mirrors, etc.) focus energy (e.g., visible spectrum energy, infrared spectrum energy) at different locations depending upon the wavelength of the energy. This focusing difference may be compensated for (i.e., so as to focus both IR energy and visible energy on the same focal plane) in optical elements of a multi-band FPA system using color correction provided by one or more optical elements.

In one exemplary embodiment, a color-correcting chopper may be employed to provide color correction to a multi-band FPA system. In such an embodiment, a multi-focusing color-correcting optical chopper may be placed in the optical train of a FPA system (e.g., in a manner such as illustrated for optical chopper 1702 in FIG. 17A). As shown in FIG. 17C, such a color-correcting chopper may be configured, for example, so that a first portion (e.g., one half) 1722 of the chopper 1702 focuses IR energy on the focal plane of the FPA, while a second portion (e.g., other half) 1724 of the chopper 1702 focuses visible energy on the focal plane of the FPA.

A color-correcting chopper may be similarly configured for other multi-band FPA configurations, e.g., a combination of mid-wave IR (about 3 to about 5 microns) and long-wave IR (about 8 to about 12 microns) detection capability that is integrated into a single dual-band FPA; a combination of short-wave IR (about 1 to about 3 microns) and long-wave IR (about 8 to about 12 microns) detection capability that is integrated into a single dual-band FPA; a combination of short-wave IR (about 1 to about 3 microns) and mid-wave IR (about 3 to about 5 microns) detection capability that is integrated into a single dual-band FPA; combination of short-wave IR (about 1 to about 3 microns), mid-wave IR (about 3 to about 5 microns), and long-wave IR (about 8 to about 12 microns) detection capability that is integrated into a single tri-band FPA; combination of short-wave IR (about 1 to about 3 microns), mid-wave IR (about 3 to about 5 microns), long-wave IR (about 8 to about 12 microns); and visible wavelength detection capability that is integrated into a single quad-band FPA; etc.

For example, still referring to FIG. 17C, in a case where optical components are configured to focus visible energy (but not IR energy) on the focal plane of a dual-band FPA, a first portion 1722 of the color-correcting chopper 1702 may be clear, transparent or otherwise “open” with no material contained therein to allow all energy (including visible energy focused on the focal plane of the FPA) to pass through to the FPA. A second portion 1724 of the same chopper 1702 may be configured to be opaque to visible energy while at the same time correcting the optical path to focus IR energy on the focal plane of the FPA. Such a configuration may be achieved, for example, by using a micro-lens/es or lenslets formed from silicon. In such a configuration, when the first portion 1722 of the chopper is aligned within the optical path of the FPA so that the FPA is viewing the clear or “open” first portion 1722 of the chopper, the visible energy is in focus on the focal plane of the FPA and the IR energy is defocused (diffused). When the second portion 1724 of the chopper is aligned within the optical path of the FPA so that the FPA is viewing the second portion 1724 of the chopper, the visible energy is blocked and the IR energy is in focus on the focal plane of the FPA. Such a configuration may be implemented to provide the visible components of the FPA with a focused visible image and a visibly blank reference, and it provides the IR components of the FPA with a focused IR image and an IR diffused image. In this and similar embodiments employing choppers with multi-portion configurations, a first radiation spectrum (e.g., visible spectrum) and a second radiation spectrum (e.g., IR spectrum) may be read out (e.g., alternately read out) from the corresponding components of the FPA (e.g., the corresponding visible and IR components of the FPA) in synchronization and in-phase with positioning of the respective first and second portions of the chopper in alignment with the optical path of the FPA.

In another exemplary embodiment, first portion 1722 of the color-correcting chopper 1702 may be manufactured of silicon-based material to block visible and near IR energy, while at the same time, passing other IR energy. In such an embodiment, a second portion 1724 of the same chopper 1702 may be manufactured of glass to pass visible and near IR energy, while at the same time blocking other IR energy.

In yet another exemplary embodiment, first portion 1722 of the color-correcting chopper 1702 may be additionally or alternatively provided as a material of different thickness as a second portion 1724 of the same chopper 1702 so as to focus particular energy wavelengths as different points relative to a FPA, and/or to selectively pass energy of different wavelengths. In yet another exemplary embodiment, a color-correcting chopper 1702 may be provided having at least two portions of different thickness that act to focus energy of two different wavelengths received from an optical train onto the focal plane of a multi-band FPA. For example, a first portion (e.g., one half) 1722 of such a chopper 1702 may be configured with an IR-transmissive material of suitable thickness to focus IR energy of a first IR wavelength on the focal plane of the FPA, while a second portion (e.g., other half) 1724 of the same chopper 1702 may be configured with an IR-transmissive material of suitable thickness to focus IR energy of a second IR wavelength on the focal plane of the FPA. To illustrate, a dual-band FPA may be provided that has detection capability for both short-wave IR energy (about 1 to about 3 microns) and long-wave IR energy (about 8 to about 12 microns), and having optical train components that without correction do not focus either short-wave IR energy or long-wave IR energy on the focal plane of the dual-band FPA. In such a case, a first portion 1722 of a color-correcting chopper 1702 present between the optical components and the dual-band FPA may be an IR-transmissive material (e.g., a silicon-based material) of a first thickness that acts to focus short-wave IR energy received from the optical components on to the focal plane of the dual-band FPA, and a second portion 1724 of the same color-correcting chopper may be an IR-transmissive material (e.g., a silicon-based material) of a second thickness that acts to focus long-wave IR energy received from the optical components on to the focal plane of the dual-band FPA to allow all energy (including visible energy focused on the focal plane of the FPA) to pass through to the FPA.

It will thus be understood that a color-correcting chopper may be provided having a plurality (e.g., two or more, three or more, four or more, etc.) of different portions configured for focusing energy of a corresponding plurality of different energy wavelengths received from an optical train onto the focal plane of a multi-band FPA configured with detection capability for the corresponding plurality of different energy wavelengths. Moreover, different portions of the color-correcting chopper may be configured in any manner suitable for focusing a respective energy wavelength on to the focal plane of a multi-band FPA. In this regard, a given energy transmissive portion of a color-correcting chopper may differ from other energy-transmissive portions of the color-correcting chopper by virtue of the absence or presence of a selected energy-transmissive material, the type/s or combination of type/s of selected energy-transmissive material, the thickness of energy-transmissive material, etc. Furthermore, it will be understood that color-correcting chopper may alternatively have a plurality (e.g., two or more, three or more, four or more, etc.) of different portions configured for focusing energy of a corresponding plurality of different energy wavelengths received from an optical train onto multiple (e.g., non-integrated) detectors configured with detection capability for the corresponding plurality of different energy wavelengths.

While the invention may be adaptable to various modifications and alternative forms, specific embodiments have been shown by way of example and described herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. Moreover, the different aspects of the disclosed systems and methods may be utilized in various combinations and/or independently. Thus the invention is not limited to only those combinations shown herein, but rather may include other combinations. 

1. An infrared detector element, comprising: a microbolometer infrared radiation detector structure, said microbolometer infrared detector structure comprising a lead metal reflector; wherein said lead metal reflector comprises an at least partially exposed top metal layer of read out integrated circuitry (ROIC) that is configured as said lead metal reflector for said microbolometer infrared detector structure.
 2. The infrared detector element of claim 1, further comprising at least one input pad for said ROIC, said input pad comprising a portion of said at least partially exposed top metal layer of said ROIC.
 3. The infrared detector element of claim 1, wherein said microbolometer infrared radiation detector structure comprises a diffractive resonant cavity (DRC) microbolometer structure.
 4. The infrared detector element of claim 1, wherein said ROIC comprises CMOS circuitry; and wherein an at least partially exposed top metal layer of said CMOS circuitry is configured as said lead metal reflector for said microbolometer structure.
 5. The infrared detector element of claim 1, wherein said ROIC is disposed on a first side of a substrate; wherein said microbolometer infrared radiation detector structure is disposed on said first side of said substrate; and wherein said ROIC further comprises: at least one additional metal layer disposed between said at least partially exposed top metal layer and said substrate; and a planarized insulator layer disposed between said at least partially exposed top metal layer and said at least one additional metal layer; wherein said at least partially exposed top metal layer is connected to said at least one additional metal layer by an electrically conductive via interconnect that extends through said planarized insulator layer between said at least partially exposed top metal layer and said at least one additional metal layer.
 6. The infrared detector element of claim 5, wherein said ROIC comprises CMOS circuitry.
 7. The infrared detector element of claim 5, wherein said at least partially exposed top metal layer is formed of a different material than said electrically conductive via interconnect.
 8. The infrared detector element of claim 1, wherein said ROIC is disposed on a first side of a substrate; wherein said microbolometer infrared radiation detector structure is disposed on said first side of said substrate; and wherein said ROIC further comprises: a first additional metal layer disposed between said at least partially exposed top metal layer and said substrate; a second additional metal layer disposed between said first additional metal layer and said at least partially exposed top metal layer; a first planarized insulator layer disposed between said first additional metal layer and said second additional metal layer; and a second planarized insulator layer disposed between said second additional metal layer and said at least partially exposed top metal layer; wherein said second additional metal layer is connected to said first additional metal layer by at least one first electrically conductive via interconnect that extends through said first planarized insulator layer between said second additional metal layer and said first additional metal layer; and wherein said at least partially exposed top metal layer is connected to said second additional metal layer by at least one second electrically conductive via interconnect that extends through said second planarized insulator layer between said at least partially exposed top metal layer and said second additional metal layer.
 9. The infrared detector element of claim 8, wherein said ROIC comprises CMOS circuitry.
 10. A focal plane array, comprising a plurality of infrared detector elements of claim
 1. 11. The focal plane array of claim 10, wherein an exposed surface of said at least partially exposed top metal layer is substantially and continuously planar across said detector element.
 12. A focal plane array assembly, comprising: a substrate having a first side; and a plurality of microbolometer infrared detector elements, each of said plurality of microbolometer infrared detector elements comprising a membrane suspended over said first side of said substrate and a lead metal reflector disposed on said first side of said substrate between said suspended membrane and said substrate; wherein said lead metal reflector for each of said microbolometer infrared detector elements comprises an at least partially exposed top metal layer of read out integrated circuitry (ROIC) that is configured as said lead metal reflector for said microbolometer infrared detector structure.
 13. The focal plane array assembly of claim 12, wherein each of said plurality of microbolometer infrared detector elements further comprises at least one input pad for said ROIC, said input pad comprising a portion of said at least partially exposed top metal layer of said ROIC.
 14. The focal plane array assembly of claim 12, wherein each of said microbolometer infrared detector elements comprises a diffractive resonant cavity (DRC) microbolometer structure.
 15. The focal plane array assembly of claim 12, wherein said ROIC comprises CMOS circuitry; and wherein an at least partially exposed top metal layer of said CMOS circuitry is configured as said lead metal reflector for said microbolometer structure.
 16. The focal plane array assembly of claim 12, wherein said ROIC further comprises: at least one additional metal layer disposed between said at least partially exposed top metal layer and said substrate; and a planarized insulator layer disposed between said at least partially exposed top metal layer and said at least one additional metal layer; wherein said at least partially exposed top metal layer is connected to said at least additional metal layer by an electrically conductive via interconnect that extends through said planarized insulator layer between said at least partially exposed top metal layer and said at least one additional metal layer.
 17. The focal plane array assembly of claim 16, wherein said ROIC comprises CMOS circuitry.
 18. The focal plane array assembly of claim 12, wherein said ROIC further comprises: a first additional metal layer disposed between said at least partially exposed top metal layer and said substrate; a second additional metal layer disposed between said first additional metal layer and said at least partially exposed top metal layer; a first planarized insulator layer disposed between said first additional metal layer and said second additional metal layer; and a second planarized insulator layer disposed between said second additional metal layer and said at least partially exposed top metal layer; wherein said second additional metal layer is connected to said first additional metal layer by at least one first electrically conductive via interconnect that extends through said first planarized insulator layer between said second additional metal layer and said first additional metal layer; and wherein said at least partially exposed top metal layer is connected to said second additional metal layer by at least one second electrically conductive via interconnect that extends through said second planarized insulator layer between said at least partially exposed top metal layer and said second additional metal layer.
 19. The focal plane array assembly of claim 18, wherein said ROIC comprises CMOS circuitry.
 20. The focal plane array assembly of claim 12, wherein an exposed surface of said at least partially exposed top metal layer is substantially and continuously planar across an array area of said focal plane array.
 21. A wafer-level packaged focal plane array assembly, comprising: a device wafer, said device wafer comprising said substrate and said focal plane array assembly of claim 12; and a lid wafer, said lid wafer being at least partially transparent to infrared radiation and being assembled to said device wafer so that said lid wafer allows infrared radiation to reach said focal plane array assembly through said lid wafer.
 22. The wafer-level packaged focal plane array assembly of claim 21, wherein said lid wafer is sealingly assembled to said device wafer and contains a vacuum therebetween to form a wafer-level packaged focal plane array assembly.
 23. A method of making a focal plane array assembly, comprising: providing a substrate having a first side; forming a lead metal reflector on said first side of said substrate, said lead metal reflector comprising an at least partially exposed top metal layer of read out integrated circuitry (ROIC) with an at least partially exposed and reflective upper surface; and forming a plurality of membrane structures on said first side of said substrate so that each of said membrane structures is suspended over said first side of said substrate with said at least partially exposed top metal layer of said ROIC disposed between said suspended membrane and said substrate.
 24. The method of claim 23, wherein each of said suspended membrane structures and said at least partially exposed top metal layer of said ROIC disposed between each of said suspended membrane structures and said substrate together comprise a microbolometer infrared detector element; and wherein said method further comprises forming at least one input pad for said ROIC of each of said microbolometer infrared detector elements, said input pad comprising a portion of said at least partially exposed top metal layer of said ROIC.
 25. The method of claim 24, wherein each of said microbolometer infrared detector elements comprises a diffractive resonant cavity (DRC) microbolometer structure.
 26. The method of claim 23, wherein said ROIC comprises CMOS circuitry; and wherein said method further comprises forming an at least partially exposed top metal layer of said CMOS circuitry as said lead metal reflector for said microbolometer structure.
 27. The method of claim 23, wherein said step of forming said lead metal reflector on said first side of said substrate further comprises: forming at least one additional metal layer prior to forming said at least partially exposed top metal layer; forming a planarized insulator layer after forming said at least one additional metal layer and prior to forming said at least partially exposed top metal layer so that said at least one additional metal layer is disposed between said planarized insulator layer and said substrate; forming at least one electrically conductive via interconnect to extend through said planarized insulator layer and connect to said at least one additional metal layer; and forming said at least partially exposed top metal layer after forming said planarized insulator layer so that said planarized insulator layer is disposed between said at least partially exposed top metal layer and said at least one additional metal layer and so that said at least partially exposed top metal layer connects to said at least one electrically conductive via interconnect.
 28. The method of claim 27, wherein said at least partially exposed top metal layer is a different material than said electrically conductive via interconnect.
 29. The method of claim 27, further comprising forming said electrically conductive via interconnect during a first processing step, and forming said at least partially exposed top metal layer during a second processing step; wherein said first and second processing steps are different processing steps.
 30. The method of claim 27, wherein said ROIC comprises CMOS circuitry.
 31. The method of claim 23, wherein said step of forming said lead metal reflector on said first side of said substrate further comprises: forming a first additional metal layer prior to forming said at least partially exposed top metal layer; forming a second additional metal layer after forming said first additional metal layer and prior to forming said at least partially exposed top metal layer; forming a first planarized insulator layer having at least one first electrically conductive via interconnect extending therethrough after forming said first additional metal layer and prior to forming said second additional metal layer so that said first additional metal layer is disposed between said first planarized insulator layer and said substrate and so that said first and second additional metal layers are connected by said at least one first electrically conductive via interconnect; forming a second planarized insulator layer after forming said second additional metal layer and prior to forming said at least partially exposed top metal layer so that said second additional metal layer is disposed between said second planarized insulator layer and said first planarized insulator layer; forming at least one second electrically conductive via interconnect to extend through said second planarized insulator layer and connect to said at second additional metal layer; and forming said at least partially exposed top metal layer after forming said second planarized insulator layer so that said second planarized insulator layer is disposed between said at least partially exposed top metal layer and said second additional metal layer and so that said at least partially exposed top metal layer connects to said at least one second electrically conductive via interconnect.
 32. The method of claim 31, wherein said ROIC comprises CMOS circuitry.
 33. The method of claim 23, further comprising planarizing an exposed surface of said at least partially exposed top metal layer to be substantially and continuously planar across an array area of said focal plane array.
 34. A method of making a wafer-level packaged focal plane array assembly, comprising: providing a device wafer, said device wafer comprising said substrate and said focal plane array assembly of claim 23; providing a lid wafer, said lid wafer being at least partially transparent to infrared radiation; and assembling said lid wafer to said device wafer to form said wafer-level packaged focal plane array assembly, and so that said lid wafer allows infrared radiation to reach said focal plane array assembly through said lid wafer.
 35. The method of claim 34, further comprising assembling and sealing said lid wafer to said device wafer in the presence of a vacuum so that a vacuum is sealingly contained between said lid wafer and said device wafer to form a wafer-level vacuum packaged focal plane array assembly. 